1. Field of the Invention
The present invention relates generally to semiconductor packages and fabrication methods thereof, and more particularly, to a carrier-free semiconductor package and a fabrication method thereof.
2. Description of Related Art
Conventionally, there are various kinds of semiconductor packages that use lead frames as chip carriers. Therein, quad flat packages (QFPs) have outer leads for electrical connecting to external devices while quad flat non-leaded (QFN) semiconductor packages dispense with outer leads to reduce the package size. However, limited by encapsulant thickness, the entire height of the QFN semiconductor packages cannot be further reduced to follow the trend of developing thinner and lighter semiconductor devices. Therefore, carrier-free semiconductor packages are developed, which are much thinner and lighter than the conventional lead frame type semiconductor packages.
FIG. 1 shows a carrier-free semiconductor package as disclosed by U.S. Pat. No. 5,830,800. Referring to FIG. 1, the carrier-free semiconductor package is fabricated through the steps of: forming a plurality of electroplated solder pads 12 on a copper plate (not shown); disposing a chip 13 on the copper plate and electrically connecting the chip 13 to the electroplated solder pads 12 through a plurality of bonding wires 14; performing a molding process to form an encapsulant 15; removing the copper plate by etching to expose the electroplated solder pads 12; forming a solder mask layer 11 to define positions of the electroplated solder pads 12 for implanting solder balls 16 to the electroplated solder pads 12 so as to provide a package without a chip carrier. Related techniques are also disclosed in U.S. Pat. Nos. 6,770,959, 6,989,294, 6,933,594 and 6,872,661.
However, the thickness of the electroplated solder pads 12 is only about 1 to 5 μm and the electroplated solder pads 12 has a poor adhesion with the encapsulant 15, which easily leads to a problem of delamination between the electroplated solder pads 12 and the encapsulant 15 and even causes cracking of the bonding wires 14. Further, a costly metal such as gold or palladium is required to form an etching resist layer when the copper plate is removed by etching, thereby increasing the fabrication cost.
In view of the above-described drawbacks, U.S. Pat. No. 6,498,099 discloses another method for fabricating a carrier-free semiconductor package, as shown in FIGS. 2A to 2F, which comprises the steps of: providing a copper plate 20 and half-etching an upper surface of the copper plate 20 so as to form a die pad 21 and a plurality of solder pads 22; plating a nickel or silver layer 203 on the entire upper surface of the copper plate 20; disposing a chip 23 on the die pad 21 and electrically connecting the chip 23 and the solder pads 22 through a plurality of bonding wires 24; forming an encapsulant 25 to cover the chip 23, the solder pads 22 and the upper surface of the copper plate 20; performing an etching process to a lower surface of the copper plate 20 so as to remove a portion of the copper plate, thereby exposing the encapsulant 25; and mounting a plurality of solder balls 26 on a lower surface of the solder pads 22 so as to form a carrier-free semiconductor package.
The above-described fabrication process uses a nickel or silver layer instead of using gold or palladium as an etching resist layer to reduce the fabrication cost. However, since the nickel or silver layer has a poor adhesion with the encapsulant, delamination is easy to occur therebetween under a thermal stress so as to cause permeation of moisture. Further, in the case the package that is already soldered to a printed circuit board 27 needs to be reworked, the solder pads 22 are easy to release from the package due to the poor adhesion between the encapsulant 25 and the silver layer as shown in FIG. 2F, thereby making the entire package become useless. Furthermore, since die-bonding, wire-bonding and molding processes are respectively performed on the half-etched copper, the thickness of the half-etched copper plate has been reduced by half, and thus the half-etched copper plate is so weak and pliable that it is not suitable for transportation and warpage of the copper plate easily occurs under a thermal effect. Moreover, as I/O count increases, wire crossing can easily occur to the array-arranged solder pads 22, thereby resulting in a problem of short circuit.
Therefore, it is imperative to provide a semiconductor package and a fabrication method thereof so as to reduce the fabrication cost and avoid the conventional problems of transportation difficulty, delamination and short circuit.